Input/output system



March 25, 1969 D. R. BERNIER INPUT/OUTPUT SYSTEM l of 12 Sheet Original Filed Oct. 23, 1965 INVENTOR. Y 774/67 Pffrff March 25, 1969 D. R. BERNIER 3,435,419

INPUT/OUTPUT SYSTEM INVENTOR. -lT-wM/mw March 25, 1969 D. R. BERNIER 3,435,419

INPUT/OUTPUT SYSTEM original Filed oct. 25, 1965 sheet 3 of 12 INVENTOK A W0 774/] )Y Ee rr/fc 7 March 25, 1969 D. R. BERNIER 3,435,419

INPUT/OUTPUT SYSTEM original Filed Oct. 23. 1965 sheet 4 of 12 per m l asfixia-2:51 A,

:Ae/z

zu: 5 un 22A( .zen

AMJ' ,2351

(4 rf :au

Mq ,una

lilo

March 25, 1969 D. Rl BERNIER INPUT/OUTPUT SYSTEM Sheet Uriginal Filed Oct. 23, 1965 INVENTOR. .Do 714// )Y 7 *gt/Q, /7 annif/5f March 25, 1969 D. R. BERNIER INPUT/OUTPUT SYSTEM Original Filed Oct. 23, 1965 Sheet L of 12 March 25, 1969 D. R. BERNIER 3,435,419

INPUT/OUTPUT SYSTEM original Filed oct. 2:5, 1965 sheet 7 of 12 .l fr; 174

/Mp [au I MM 1 Il la t E. 4 Mm l ,207742.97 )Y 567'?? IC7' March 25, 1969 D. R. BERNIER 3,435,419

INPUT/OUTPUT SYSTEM March 25, 1969 D. R. BERNIER 3,435,419

INPUT/OUTPUT SYSTEM original Filed oct. 2s, 1965 sheet 9 of 12 lil- 2% /dm March 25, 1969 D, R, BERNlER 3,435,419

INIUT/OUTPUT SYSTEM Original Filed Oct. 23, 1965 Sheet /0 of 12 Illa 207i linfa 2me 61e d l l @MME :@QLJ

1E /J7 INVENTOR.

March 25, 1969 D. R. BERNIER 3,435,419

INPUT/OUTPUT SYSTEM Original Filed Oct. 23, 1965 Sheet or l2 fd@ /A7/ w -L /w I I ma 'I I I I ,arr 323m 7d/Mig@ March 25, 1969 D. R. BERNIER INPUT/OUTPUT SYSTEM Sheet Original Filed Oct. 23, 1965 NRM vw RFR JWNNW United States Patent Oftice 3,435,419 Patented Mar. 25, 1969 3,435,419 INPUT/OUTPUT SYSTEM Donald R. Bernier, Detroit, Mich., assignor, by mesne assignments, to Intercontinental Systems, Inc., Los Angeles, Calif., a corporation of California Continuation of application Ser. No. 503,861, Oct. 23,

1965. This application Oct. 31, 1966, Ser. No. 590,761

Int. Cl. Gllh 13/00 U.S. Cl. S40-172.5 7 Claims ABSTRACT F THE DISCLOSURE There is herein disclosed an automatic data processing system for transferring data information from a data input device to a data utilizing device wherein portions of columns of bits are divided into X address digital pulses and a second portion of each of the columns is divided into Y address digital pulses.

This application is a continuation of my prior copending application Ser. No. 503,861 led Oct. 23, 1965, for Input/Output System.

This invention relates generally to business machine systems and more specifically to data processing systems to be utilized in conjunction with business machines which are adapted to receive, transfer and utilize variously coded input data in the form of coded information signals from a plurality of input data sources wherein the output coded information may be fed to a plurality of data utilizing systems which may be selectively actuated or the system may be utilized as a terminal system and associated with a master data processing system for extending the capabilities of the terminal system.

ln general the principles of the present invention are shown embodied, for illustrative purposes only, in an automatic writing system, the system including a plurality of data inputs of differing code configurations. The data is adapted to be transferred through a data processing system, thus providing coded output signals to a plurality of output data utilizing devices, which may also be of diftering code configurations. ln data processing systems of the type with which the invention is concerned, it is desii-able to provide an operator with a complete system capable of accepting coded data inputs in any code configuration and utilizing a variety of data input devices, as for example, a reader unit, an external data input system, typewriter units and the like. Similarly, it is desirable to permit the operator to process the data such that the data may be stored in a variety of forms, such as a page print. cards, tapes and other coded data forms, or as coded signals.

Thus, the form of the data being presented to the utilizing device may take a variety of forms, as for example, coded data output signals for use in providing a coded output data form, alpha-numeric and function coded signals for use in a page print output means, or purely a parallel data bit output system wherein parallel bits are presented to the utilizer in a coded signal form. With the system of the present invention, a plurality of input sources of data information may be supplied to the data processing system as for example, in the form of an external input of a first code configuration which may take the form of a reader unit or other type of data signal producing means. A second data input source is provided in the form of a reader unit of a second code configuration. Also, a third input source in the form of a conventional automatic typewriter unit having keyboard encoding means for encoding the actuation of the bails within the typewriter unit and also means is provided to encode certain functions provided on the keys of the keyboard and encode these functions whether they be system functions or machine functions in a third code configuration. It is to be understood that further data input sources may be provided in any number in accordance with the requirements of the user.

The data input flow is fed through a common code conversion system whereby each of the plurality of code configurations is made compatible, each with the other or with a further code, and fed through the system to provide a single output code configuration from the code converter. However, the system is provided with a plurality of data utilizing devices which may require different code configurations. Accordingly, a second code conversion system is provided to convert the code being utilized in the system into a plurality of output code configurations, thereby conforming the code of the output data signals to the code configuration of the particular code utilizer. ln the representative illustration, the code utilizers may take the form of a page printer, for example, an automatic typewriter or the like, and requiring a rst type of code configuration. Also, the output devices may include a punch output requiring a second type of code configuration and a third type of output in the form of data signals may be provided to an external output device requiring a third code configuration.

In accordance with certain other principles of the present invention, features have been provided to minimize the number of errors generated within the system itself in order to increase the reliability of the data being processed through the system. Accordingly, certain principles of the invention, as embodied in the representative illustration, include a system for accepting data input of a particular code configuration and bypassing the conversion system in order to provide data output which is of an identical code configuration to that received. In this way, the heretofore utilized method of accepting a code of a first configuration and, through successive code conversions and reconversions, outputing the first code configuration to a utilizing device has been eliminated. In systems of the prior art type, certain errors are generated within the system due to the repeated encoding and decoding of the data signals alleviating the inherent errors generated in such systems. ln the system of the present invention, as representatively illustrated, the inherent errors generated in the prior art systems are alleviated, due to the fact that the data flow is shunted around the encoding and decoding system in the situation where the desired data output code configuration is identical to that received at the data input.

Also, certain developments have created a demand for a terminal data processing system which is capable of `being associated with a master common data processing system wherein data information may be fed into the terminal system and transmitted to the central data processing system through an interface. Accordingly, a system has been provided wherein the terminal unit is capable of receiving data in any particular code configuration and transforming that data into a code configuration which is compatible with a master data processing system. Further, means has been provided whereby the master control system may control the operation of the terminal unit in response to certain signals generated within the master data processing system. Similarly, the terminal system is capable of generating certain system ready signals. In this way, the synchronism of the terminal data system may be kept apace with the synchronism of the master data processing system in accordance with either the operation of the data terminal system or the master data processing system. The system, embodying certain principles of the present invention, has been provided with the necessary circuitry to present certain control signals to a master data processing system which may be used in association with the terminal system, these signals being made responsive to certain operations of the terminal system. Accordingly, the master data processing system is capable of controlling the operation of the data of the terminal system and the terminal system is capable of indicating to the master data processing system when the terminal is ready to receive or transmit data.

Accordingly, it is one object of the present invention to provide an improved data processing system which has improved reliability and speed characteristics.

It is another object of the present invention to provide an improved data processing system which is capable of assimilating data inputs of varying code configurations with greater reliability.

It is still a further object of the present invention to provide an improved data processing system which may be programmed to accept data inputs having varying data code configurations and converting these code configurations to a common system code.

It is another object of the present invention to provide an improved code translation system which is highly versatile.

It is still another object of the present invention to provide an improved data processing system which is capable of receiving data inputs from a plurality of input sources having varying code configurations and transforming the code configurations of the input sources to varying output data code contigurations.

1t is still a further object of the present invention to provide an improved data processing system which is capable of receiving a plurality of sources of input data of varying configurations and selectively converting the code of certain of the data input sources and selectively transmitting other code configurations of other data input sources of a plurality of output devices and selectively connecting the data sources to certain output devices in accordance with the particular code configuration.

lt is still a further object of the present invention to provide an improved terminal data processing systcm which may be reliably interconnected with a master central data processing system through suitable interfacing circuits to provide compatability between the two systems.

lt is still another object of the present invention to provide an improved terminal data processing system which is adapted to be associated with a master central data processing system through a suitable interfacing system wherein the master data processing system is capable of controlling the operation of the terminal system and the terminal system is capable of generating response signals for the central data processing system to indicate the condition of the terminal data processing system, thus increasing the reliability of the systems.

lt is still a further object of the present invention to provide an improved data processing system which is capable of receiving inputs of varying code configurations from different sources and converting the input code configurations to a common code prior to storage of the information within the system.

It is still a further object of the present invention to provide an improved method of clocking information into a data processing system and particularly into a storage subsystem thereof.

It is still a further object of the present invention to improve methods of and apparatus for encoding machine and system functions in a data processing system.

It is still a further object of the present invention to provide an improved method and apparatus for selectively enabling certain operations of a data processing system in response to selected modes of operation of the system.

lt is still a further object of the present invention to provide an improved apparatus for alleviating spurious signals generated in certain switch actuated operations of a data processing system.

It is still another object of the present invention to improve the reliability of a data processing system in providing control and signal pulses for system and machine functions of the data processing system, wherein the system is not disabled during system and machine functions of extremely long duration.

It is still another object of the present invention to provide improved data processing system wherein the system for enabling the effect of character operations of the data processing operation in response to the operations of certain portions of the data processing mechanism are greatly enhanced.

It is still another object of the present invention to provide an/improved data processing system wherein the dilatory effects of electrical and/or mechanical switch noise is alleviated by a method of integrating certain portions of the switch pulse.

It is still another object of the presenpinvention to improve the storage capabilities of a data processing system wherein the input data information is impressed on a storage circuit by enabling a transfer means with a persisting enabling pulse, thereafter resetting the storage circuits and clocking information into the storage circuits through the transfer means, whereby the enabling pulse disables the transfer means from passing further pulses therethrough.

It is still another object of the present invention to provide a greatly simplified system of programming a data processing system to accept incompatible codes from various data input sources.

lt is still a further object of the present invention to enhance the characteristics of a decode system by segregating certain information channels on a multichannel, parallel data, writing system code into a plurality of segments for balancing the input circuits of the decode system.

It is still another object of the present invention to improve the methods of converting a plurality of coded digital input signals into a single digital signal, the single signal representing the combination of the coded input signals.

lt is still another object of the present invention to improve the methods of deriving a parallel bit, coded signal configuration from a single digital input signal for use in a data processing system.

lt is still another object of the present invention to provide an improved system adapted to be utilized in a data processing system for selecting one of a plurality of input sources of data information signals wherein the undesired source of signal is inhibited by a selector signal generated in response to certain operations of the writing system.

It is still a further object of the present invention to provide an improved method and apparatus for selecting desired logic circuits to be energized by a particular code conguration by sensing a selected portion of the code and generating selected enabling signals in response to the selected codes.

It is still a further object of the present invention to improve the system of clocking information into a data processing system whereby only a single operation is required to synchronize a certain plurality of operations of the system.

It is still a further object of the present invention to improve clocking systems for use in a data processing system wherein a single operation of the system is utilized in timing a certain plurality of operations of the system and wherein means is provided to inhibit certain portions of the sequential operation of the clocking system to adapt the system to operations of longer duration than certain other operations ofthe data processing system.

It is still another object of the present invention to improve the clocking systems utilized in an automatic data processing system wherein means is provided for generating a plurality of sequential time duration pulses of a predetermined spacing and includes means for lengthen4 ing the spacing between certain of the pulses.

It is another object of the present invention to improve the clocking systems as described above wherein the clocking system further includes means for storing the end of one of the pulses and feeding the stored pulse to a pulse transfer means and further providing means for selectively enabling and disabling the transfer means.

It is another object of the present invention to improve clocking systems utilized in conjunction with data processing systems wherein means is provided for generating a plurality of sequentially timed pulses of predetermined timed spacing, the timing system being adapted to be started in response to a system operation and one of the sequential pulses being stored and transferred to a subsequent pulse generator through a pulse transfer means, In the timing system, the pulse transfer means is selectively enabled and disabled to lengthen the duration between the stored pulse and the subsequent pulse and further includes means for resetting the storage device in response to the generation of the subsequent pulse in the same timing sequence or a previous pulse in a subsequent timing sequence.

It is still a further object of the present invention to provide an improved and highly reliable automatic feed system for data information storage means.

It is still another object of the present invention to provide an improved and highly reliable data information automatic feed system including storage means for continuously feeding the data storage means through the automatic feed system until the storage means is reset.

It is still another object of the present invention to provide a highly reliable data information automatic feed system wherein means is provided for automatically resetting the storage means.

It is another object of the present invention to provide a data processing system which is adapted to be utilized in conjunction with another data processing sys' tem with an improved means for signaling a selected mode condition of the first data system.

Other objects, features, and advantages of the present invention will become apparent from the subsequent description and the appended claims, taken in conjunction with the accompanying drawings, in which:

FIGURE 1 is a block diagram schematically illustrating a complete data processing system including an input section comprising an external input, a reader input and a typewriter unit, a dual conversion code converter section, and an output section including a printer output, an external output and a punch output;

FIGURE 2 is a block diagram schematically illustrating the relative interconnections between the clock pulse t generator system, the mode I and mode II control systems and the feed card system;

FIGURE 3 is a block diagram schematically representing the interconnections between a reader control circuit, a print punch circuit, a select register circuit and a response generator circuit;

FIGURE 4 is a schematic diagram of a preferred embodiment of a monostable pulse producing means, in the form of a single shot multivibrator, adapted to be utilized in certain positions of the data processing system;

FIGURE 5 is a schematic diagram of a preferred form of a power driver circuit which is adapted to be utilized in conjunction with certain devices having large current requirements;

FIGURE 6 is a schematic diagram of a preferred form of gating device, specifically illustrated as a norgate, which is adapted to be utilized in the logic circuits of a data processing system;

FIGURE 7 is a schematic diagram of another preferred form of monostable pulse producing circuit which is responsive to a single input pulse thereby eliminating subsequent input pulses for a predetermined length of time. The monostable pulse producing circuit is representatively illustrated as a switch trigger circuit which is adapted to be utilized in providing an output pulse in response to the actuation of certain switches utilized in a data processing system;

FIGURE 8 is a schematic diagram of a preferred form of gating circuit specically including an integrating gate which is adapted to integrate a series of input pulses to produce a single output pulse;

FIGURE 8a is a schematic diagram of another preferred form of gating circuit and particularly illustrating a diode orgate;

FIGURE 9 is a schematic diagram of a preferred emitter follower circuit and specifically is illustrated as an NPN emitter follower;

Similarly, FIGURE l0 is an illustration of a second preferred form of emitter follower circuit but utilizing a PNP type transistor;

FIGURE l1 is a schematic diagram of a preferred form of amplifier which may be utilized in certain encoding circuits of a data processing system;

FIGURE l2 is a schematic diagram of a preferred form of diiferentiator circuit specifically illustrating a plural input, single output differentiator utilized in producing a single output pulse in response to any one of a plurality of input signals; and

FIGURES 13 to 25 comprise a schematic diagram of the details of a complete data processing system incorporating certain features of the present invention in which:

FIGURE 13 is a schematic diagram of the input section of the data processing system and particularly illustrating the input circuit configurations of an external input source of data, a reader unit utilized as a source of input data, and a portion of a keyboard source of input data for encoding certain switch functions on the keyboard of a typewriter' unit;

FIGURE 14 is a schematic diagram illustrating the remainder of the keyboard input logic circuits specifically including encoding circuits for the certain machine functions and bail switches of the typewriter unit and further illustrtating the storage register logic circuit including the clocking circuits for clocking information into the storage register circuit;

FIGURE 15 is a schematic diagram of an X address logic circuit, a Y address logic circuit, and a block diagram illustrating the relationship of the X and "Y address logic circuits with a decode matrix circuit, a print encode matrix circuit and a punch encode matrix circuit;

FIGURE 16 is a schematic diagram illustrating a portion of the specic circuit details of the decode matrix circuit of FIGURE l5 wherein suicient details of the circuit are illustrated to extrapolate the remainder of the circuit;

FIGURE 17 is a schematic diagram illustrating a portion of either the print encode matrix or the punch encode matrix of FIGURE l5, the two being identical, wherein the remainder of the circuit is substantially identical to that shown insofar as providing output codes to the respective output channels are concerned;

FIGURE 18 is a schematic diagram illustrating the print encode output logic circuit which is adapted to receive coded signals from the print encode matrix and feed these signals to the print output system of the data processing system;

FIGURE 19 is a schematic diagram illustrating an output decode I logic circuit and an output decoded II logic circuit which are utilized in decoding both the machine functions and the system function codes respectively;

FIGURE 2O is a schematic diagram illustrating the output logic circuits for the machine function solenoid system and the bail solenoid system which are utilized in actuating certain operative portions of a typewriter unit which may be incorporated into a data processing system;

FIGURE 21 is a schematic diagram illustrating the punch output I logic circuit and the punch output logic circuit, thc logic circuits being adapted to receive input signals from both the punch encode matrix and directly 7 from the decode register circuit described in conjunction with FIGURE 14;

FIGURE 22 is a schematic diagram illustrating the punch output circuit and particularly the punch output logic circuit and the solenoid circuit thereof;

FIGURE 23 illustrates the mode control I logic circuit and the mode control II logic circuit which is adapted to control the mode of the data processing system in response to signals generated either within the system or from an external system;

FIGURE 24 is a schematic diagram illustrating a reader control circuit which is adapted to provide clock start signals to start the clocking circuit and also an external input interlock circuit to provide an interlock signal in response to the operation of the data processing system; and

FIGURE 25 is a schematic diagram illustrating the print punch circuit which is adapted to enable or disable the printing and punching systems of the data processing systems and also is adapted to provide ready signals to a select register circuit wherein the select register circuit generates control signals to be fed to a response generator circuit also illustrated in FIGURE 25, the response generator circuit providing an output signal to a central data processing system to indicate the readiness of the terminal data processing system.

DESCRIPTION OF THE BLOCK DIAG RAM Referring now to the drawings, and particularly to FIGURES l, 2 and 3, there is illustrated a block diagram of one preferred embodiment of an input/output system incorporating certain principles of the present invention. FIGURES 1, 2 and 3 illustrate the flow of data from a plurality of input units `through a storage register section, a dual conversion code converter 102, thence to a plurality of output sections including a print output 104 and a punch output 106. The input section 100 includes an external input which may take the form of any source of parallel bit, coded signals which normally would have from one to eight channels, as is Common in the art. One such external source of coded data signals may take the form of an external reader unit which is capable of providing bits of data in a parallel form, the bits being fed to a decode register 112, 113 through a cable 114. The decode register stores the parallel bits of data prior to their being passed forward into the code conversion portion 102 of the system. The external input 110 and the decode register 112, 113 are interconnected by means of a plug and jack arrangement whereby the incoming code from the input 110 may be prearranged in its storage in the decode register section 112, 113 by merely changing the connections between the input 110 and the decode register 112, 113.

The system has been provided with a second input from a reader unit 118 which is generally of the conventional type, having a plurality of one to eight channels. In the preferred embodiment, the reader unit generally takes the form of a plurality of photo diodes (not shown) forming the pickup which is capable of sensing holes or lack of holes punched in a coded information means, in the form of a tape or card. In is to be understood that the system does not require any particular type of pickup and may include a magnetic sensing system for sensing coded magnetic portions or a support device or any other type of data storage means. The output of the reader unit is fed through ia reader amplifier to provide the necessary current to drive the curcuit components in the decode register. The photo diodes and reader amplifiers have been representatively illustrated as a reader board 120, the output of which is fed to the decode register 112, 113 through a cable 122. Thus, the data bits from the reader unit 118 are stored in the decode register unit 112, 113 until such time as certain control functions within the system strobe the information forward from the decode register unit.

A third input to the decode register 112, 113 has been provided from a printed character and machine function unit which may take the form of an electric typewriter or the like, and the coded information from a keyboard encoding circuit 126 is fed to the decode register units 112, 113 by means of a plurality of cables 128, 130. As is well known in the art, the common electric typewriter unit 126 comprises a set of bail switch means for encoding the characters of the typewriter unit, which encoding means has been shown for illustrative purposes as a plurality of bail switches. The particular bail switches are actuated by the keys of the keyboard and for each key a particular code of bail switches has been provided, hereinafter referred to as printer output switch means 130, the plurality of coded signals being fed to a keyboard encode circuit 1,32 which provide the necessary coded signals for the decode registers 112, 113.

The printer output switches 130 also include a plurality of machine functions which are inherent in the operation of the typewriter unit, as for example, index, space, tab, upper shift, lower shift, etc. A plurality of switches have been provided to sense the movement of certain portions of the typewriter unit which are utilized in performing the above mentioned machine functions thereby providing an output signal which is indicative of the occurrence of these machine functions. These switches, along with the printer output switch means, may take the form of reluctance switches, read switches or `the like. The output of the machine function output switches is fed to the keyboard encode circuit 132 through the cable 134, thereby encoding the particular machine functions being performed.

The typewriter unit has been further provided with certain control switches as, for example, start-stop, printer on, punch on, form feed, keyboard on, etc. switches, and in order to punch these machine functions into a punch unit and to operate the mechanisms in the respective output or input unit, it is necessary that the functions be encoded into a code which is compatible with the output punch unit or the particular device to be controlled. Accordingly, a plurality of control switches 138 have been provided which provide a coded output signal upon the actuation of the particular system function codes. These output signals fed to a plurality of switch triggers 140 by means of a cable 142, the switch triggers providing a single output signal for each actuation of the control switches 138. The switch triggers 140 have been provided to eliminate any switch bounce which may be present in the system function control switches, thereby eliminating spurious signals from the system control switches. The output of the switch triggers 140 are fed to an encoding circuit in the form of a keyboard encode logic circuit 142 which receives the system function signal and encodes the signal into a compatible code conguration with the keyboard encode logic circuit 132. The output of the function keyboard encode circuit 142 is fed to the keyboard encode circuit 132 by means of a cable 146.

The information stored in the decode register 112, 113 has been split into two sections consisting of decode register I 112, which is fed information data from four of the channels of the input sources and includes bits in decode register output channels 1, 2, 3 and 7, and a second decode register 1I circuit 113, which contains the second four channels or bits of information and includes decode register II circuit 113 output channels 4, 5, 6 and 8. In the preferred system, channels 1, 2 and 3 and 4, 5 and 6 are utilized as information channels, channel 7 is a parity channel, and channel 8 is an auxiliary channel for a purpose to be hereinafter explained. Output information on four output channels of the decode register I logic circuit is provided on a plurality of conductors or cable 148 and the information on the other output channels from the decode register II logic circuit 113 is provided on cable 150. The information in the decode registcrs 112, 113 is controlled by means of a plurality of clocked control signals from a clock control circuit to be hereinafter explained, whereby an initial clock control pulse is fed into the decode register circuits 112, 113 initially reset all of the circuits therein, A second clock control signal is fed into the decode register circuits 112, 113, in the preferred embodiment, which is an inversion of the original resetting clock control pulse, to allow the information being fed to the decode register circuits 112, 113 to be stored therein.

As stated above, the outputs of the decode registers 112, 113 have been broken into two components consisting of four channels each, channels 1, 2, 3 and 7 consisting of an X portion and channels 4, 5, 6 and 8 consisting of a Y portion. Referring first to decode register circuit 112, a plurality of parallel output signals are impressed on cable 148 and fed into an X address encoder 156. The X address encoder 156 converts the parallel encoded signals into a single pulse, which is indicative of the particular channels energized. For example, if an input code having a bit in channels l, 2 and 3 is received at the X address encoder 156, an output signal will be provided at a single output terminal from the X" address encoder 156. When the single output terminal is true, a bit in channels 1, 2, 3 is signified and all of the other output terminals of the X address encoder 156 will be false.

The output of the second decode register section 113 is fed to a Y address encoder 158 through the cable 150, the Y address encoder 158 being similarly interconnected to provide a single output pulse from each parallel coded input signal configuration. As stated above, channels 4, 5 and 6 are the only channels encoded in the Y address encoder 158, however, the "Y address encoder 158 may be expanded to include channel 8 by providing an additional number of circuit elements. Thus, for a parallel coded input signal configuration, a single output pulse will be provided at the output terminal and the rest of the output terminals will be false.

The outputs of the X address encoder 156 and the Y address encoder 158 are fed to a decode matrix 160 by means of conductors 162 and 164 respectively. The decode matrix is formed of a plurality of lines of input terminals, hereinafter referred to as the "X input terminals, and a plurality of columns of input terminals, hereinafter referred to as the Y input terminals. The X and Y input terminals are interconnected by a plurality of circuit elements in a matrix conguration whereby the coincidence of a single X address encoder output signal and a single Y address encoder output signal will provide a single output signal from the decode matrix 160. Thus, the decode matrix 160 provides an output signal on a particular output terminal, which corresponds to the various combinations of each of the output signals from the X address encoder and the Y address encoder 158.

Thus the eight possible coded signals from the X address encoder 156 have been combined with the eight possible codes from the Y address encoder 158 through the decode matrix 160 to a plurality of 64 output codes. Each of the 64 output codes corresponding to the encoding of either an alphanumeric character, a machine function or a system function.

The output of the decode matrix 160 is selectively interconnected with a print encode matrix 168 by means Of a cable 170, the interconnection being made through a plurality of plug and jack devices to enable the operator to selectively change the encoding of the output signals from the decode matrix 160. The 64 output signals on conductors 170 are fed to the input terminals of the print encode matrix 168 which, in the preferred embodiment, takes the form of a diode matrix having a plurality of 64 input terminals and from one to seven output terminals for each of the input terminals. The input terminals are connected to the output terminals through a plurality of diode legs whereby the input signal is broken down into its constituent parts by the provision of the necessary number of diode legs in the respective channels. For example, if an input signal indicates a bit in channels 1 through 7, a plurality of 7 diode legs will be connected to the input terminal to provide 7 output pulses at a plurality of 7 output terminals Similarly, the remainder of the input terminals are connected to the desired configuration of output terminals through similar diode legs. The output of the print encode matrix is fed to a print encode output matrix 174 by means of a plurality of conductors 176, the print encode output circuit 174 providing the necessary drive current to the output circuit.

The decode matrix is also connected to a punch encode matrix 178, which is similar in configuration to the print encode matrix 168, by means of a plurality of conductors 180. As in the situation with the print encode matrix 168, the punch encode matrix 178 is connected to the output conductors 180 of the diode matrix 160 through plug and jack devices whereby the code from the decode matrix 160 may be selectively changed through the punch encode matrix by merely shifting the interconnections between the/diode matrix 160 and punch matrix 178. Thus a separate code may be utilized for the print output as derived from the print output circuit 174 and still a further code may be utilized for the punch output as derived from a punch encode output circuit 184. The punch encode circuit 184 is connected to the punch encode matrix 178 through a plurality of conductors 186, the punch encode output circuit 184 providing sufcient driving current for the output circuit to be hereinafter explained.

Referring first to the print encode output signals, the output signals of the print encode output circuit 174 are fed to the print decode and output circuit 104 by means of a plurality of conductor 188 thereby generating coded signals to operate the various portions of a print output mode and to operate various functional portions of the system.

As seen from the above description, the output signals from the print encode output circuit 174 include coded character signals, coded machine function signals and coded system function signals, In the operation of the system, it is desirable to discriminate between the various coded signals described above to direct the respective groups of codes to the proper output device. Accordingly, each group of coded signals, as defined above, have been provided with a characteristic signal configuration in order that the system may differentiate between the various codes. In the preferred embodiment and describing only one example of a characteristics code, each alpha-numeric character code has been provided with a code configuration which does not include a channel 7 code. Thus, any output code from the print encode output circuit 174, which does not have a bit in channel 7, will be designated as an alpha-numeric character code to be directed to the printer unit itself.

Similarly, a code which designates a system function will be provided with a channel 7 code and also a bit in channel 1, and contrariwise a machine function code will `be provided with a bit in channel 7 and no bit in channel 1. The system has been provided with means for recognizing each of the three characteristics codes to direct the particular code configuration to its proper output system.

Referring first to the character codes or those without a bit in channel 7, these codes are fed through a plurality of conductors 190 to a power driver circuit 192 by means of a plurality of conductors 194, the power driver circuit providing the necessary current to actuate bail solenoids contained in a printer unit 196. The power driver circuit 192 has been provided with an enabling circuit which is energized only when there is not a bit in channel 7, thus enabling the power driver circuit for the character codes, as described above. The power driver circuit also contains a reader clutch power driver to pick the reader clutch thereby advancing the reader to the next line of codes in the coded tape. The particular control circuits sensing the presence or existence of bits in channels 1 and l 1 7 will be described in conjunction with the description of FIGURE 3.

The machine function coded signals are fed by means of a plurality of conductors 198 to an output decode circuit 200. The output decode circuit 200 receives the coded machine function signals from the print encode output circuit 174 and decodes the signals in accordance with the particular code configuration receiver to provide individual output signals for each of the machine functions such as tab, space, back space, carrier return, etc. The output signals of the output decode circuit 200 are fed through a power driver circuit 202 to the particular actuating solenoids or other actuating means contained within the printer 196 by means of a plurality of conductors 204, thereby providing the necessary driving current to actuate the machine function solenoids.

As in the situation with the power driver circuit 192, an enabling signal is fed from a circuit to be described in conjunction with FIGURE 3, which enables the machine function decode circuit in the event that a bit is absent from channel 1 and a bit is present in channel 7. The system function codes present on conductors 198 are sensed by an output decode circuit 208, which is enabled by a system function decode gating circuit similar to the enabling circuits to be described in conjunction with the character code and machine function code circuits. The system enabling circuit is energized by a bit in channels 1 and 7 as discussed above, and the output of the output decode circuit 208 is fed to the respective control circuits by means of a plurality of conductors 210, to be hereinafter described.

Referring now to the punch output codes, the coded signals from the punch code output circuit 184 are fed to a two-section punch output circuit 214, 216. The punch output circuits 214, 216 also include inputs from the decode registers 112, 113 by means of a plurality of conductors 218 and 220. The punch codes impressed on conductors 218, 220 have identical code congurations to those received at either the external input 110 or the reader unit 118. As stated above, these codes have not been encoded and subsequently decoded through the dual conversion code converter 102 due to the identity of code configuration between that required at the output and received at the input circuits. The bypassing of the decoding and encoding circuits has been provided in the event that it is desired to punch the same code in the output circuit as was received in the input circuit, thereby eliminating the possibility of error due to the encoding and decoding operation. The punch output circuits 214, 216 also include enabling input signals which permit the operator to choose which of the inputs, the punch encode output signals or the decoder register output signals, are to be fed through the punch output circuits 214, 216.

These input enabling circuits are contained in the system to be described in conjunction with FIGURE 2 and provide an enabling signal to enable either the input signals from the punch encode matrix or the signals being received from the decoder registers 112, 113 to be passed through the punch encode output logic circuit 184. The output from the punch output circuit 214, 216 is fed either to an external output circuit 224, which may take the form of an auxiliary punch unit or any other type of output unit, and the output from the punch output circuits 214, 216 are also fed to a power driver circuit 266 which provides the necessary current to drive the actuating coils in a punch unit 228.

Referring now to FIGURE 2 there is illustrated a control system for the input-output data processing system described above. The control system generally comprises a clock circuit 230, a mode l control circuit 232, a control ll mode circuit 234, and a feed card circuit 236. The operation of the above described data system is controlled by means of the clock circuit 230 which generally comprises a plurality of means for generating clock pulses which are of a specified duration and spaced one front another by a predetermined time interval. The clock circuit may be initially started by means of a plurality of start signals, as for example, a manual start signal by manually operating the keyboard, a reader clock start signal which is generated within the reader unit itself.

The clock circuit provides an initial clock pulse, hereinafter referred to as a control A clock output pulse, which is the initial starting pulse and also serves to reset the decode register system circuits 112, 113. The control A clock pulse also provides a signal to enable the decode register to store the information from the various input devices, as for example, the external input 110, the reader unit 118 or the keyboard. The clock circuit contains a pair of clock pulse generating means which generate a control A pulse and a control B pulse, the latter pulse being utilized to switch the triggers controlling the system functions such as print on, etc. The control A pulse is adapted to reset the circuits in the decode register circuits 112, 113, and also to enable the decode register circuits 112, 113 to store information being fed thereto from the various input units. The second pulse is a control B pulse, which is utilized in actuating the select register, to be hereinafter explained, and the control B pulse is further utilized in starting the control C pulse. The control C clock pulse generating circuit is utilized in clocking certain response generator functions and to synchronize the operation of the interface circuit, and the control D clock pulse generating circuit is utilized in controlling certain functions being performed in the system by providing a gating or enabling pulse for the system function solcnoids, as one example.

A feed card circuit 236 is provided and utilized in controlling the feeding of cards, tapes and other coded data storage means through the punch of the system, or to position cards within the punch unit `whereby certain codes may be punched on the card by means of a punch unit. Similarly, it is desirable to manually or automatically control the feeding of tape through the punch units and accordingly, certain circuitry has been provided in the feed card system to enable the operator to feed coded tape through the reader unit or through the punch unit. Thus, the operator controlling the terminal data processing system or a master control system is able to automatically control the feeding of coded information means through the punch unit.

The two mode control circuits 232, 234 have been provided to control the various modes of the system as for example, to enable the keyboard during the period when a manual input is being provided and to disable the reader and auxiliary input during the manual input, to control the output punch units and cycle the reader clutch in accordance with the control D signal, to correlate the various operations of the system with the operation of an interface unit, to enable the clock to be started when certain codes are generated which do not otherwise start the clock, as for example, the end of address and block signals and also to provide certain inverted codes as for example, to provide a m and a control A from the same input signal. Further examples of the functions of mode control I 232 and mode control ll 234 circuits, including the interrelation thereof and the provision of control signals to correlate the operation of the cornplete system, will be more fully explained hereinafter.

Referring now to FIGURE 3, there is illustrated a control circuit 240 which generally comprises a reader control circuit 242, a print and punch control circuit 244, a select register circuit 246 and a response generator 248. The reader control circuit 242 contains certain logic circuits to start the clock in response to the operation of the reader and also in response to certain codes generated `within the system, as for example the operation of the reader start switch, and to provide a reader ready signal to aetuate the select register circuit 246. Also, the reader control circuit provides an output pulse to signal the select register circuit 246 that the reader has been turned on. The reader control circuit further provides an interlock signal for the external input, as `will be hereinafter explained, to signal the external source of data that certain functions being performed in the terminal system have not been completed.

The printer and punch control circuit 244 provide enabling signals to be fed to the printer gate circuit and the punch gate circuit in response to printer on-ot signals and punch on-otf signals and these signals are coordinated with certain other input signals, as for example the control D pulse and an output inhibit pulse. Also, the signal to enable the machine functions circuit or output decode I circuit 200 is generated in response to the sensing of a bit in channel 1 or a lack of a bit in channel 1, as described in conjunction with output decode circuits 200, 208. Also, printer ready and punch ready signals are generated in response to a printer-on code or a printer-on switch signal in the case of the printer ready signal and a punch-on code or a punch-on switch signal in the case of the punch ready signal. These latter signals are fed to the select register to signal the select register 246 that the printer or punch has been actuated.

In the system of the present invention, means has been provided to adapt the terminal system to be interconnected with a remote master control unit which is capable of controlling the operation of the terminal system described. In certain instances, it is necessary that the system gencrate a response signal which is indicative of the selection of a particular mode of operation of the terminal system, in conjunction with the ultimate actuation of that mode. For example, if the operator of the master `unit signals the above described system to turn the reader on, it is desirable to generate a signal which tells the operator that the reader-on signal has been received and also that the reader has been turned on. To this end, the select register circuit and the response generator circuit have been interconnected to provide a response signal which tells the remote operator that the particular coded signals are being followed by the system. Thus, when the reader has been selected, the reader control circuit 242 will generate a signal which indicates that the reader has been turned on. Similarly, a reader select code is fed into the select register and both indications of the reader-on code and the reader select operation are stored and fed to a response generator. The response generator, in turn, generates a signal which is indicative of the nal turning on of the reader or other unit in response to a select signal.

DESCRIPTION OF THE COMMON CIRCUIT MODULES Referring now to FIGURES 4 to 12 of the drawings, there are illustrated a plurality of schematic diagrams depicting the common circuit modules utilized in building the data processing system to be described hereinafter. The following description of the common circuit modules is provided to facilitate the full understanding of the operation of the system as the description proceeds and to provide lbfrevity of the description inasmuch as one idescription of each circuit model will be substantially common to all the uses of that particular circuit module in the system. For purposes of simplicity, the voltage levels at various points on the conductors of any circuit will be indicated by a logical zero or one designation. For example, where the voltage at a point is approximately a minus 12 volts, the voltage level will be indicated as being a logical zero. Similarly, where the voltage at the point is approximately zero volts, the voltage level will be indicated as being a logical one signal. In each of the common circuit module gures, the schematic representation of the circuit has been illustrated along with its corresponding symbol, the symbol being placed adjacent the circuit diagram in the same ligure.

Referring now to FIGURE 4, there is illustrated a monostable pulse producing circuit, in the form of a single shot multivibrator 270, having an A input terminal 272 and a B input terminal 274, and a logical zero output terminal 276 and a logical one output terminal 278. T hc single shot multivibrator, in the preferred form, consists of a normally conducting PNP transistor 280 and a normally nonconducting PNP transistor 282 interconnected. therewith. The transistor 280 includes a collector electrode 286 connected to a negative source of potential, as for example a minus l2 volts, through a collector load resistor 288. An emitter electrode 290 is connected to ground 292 through a conductor 294.

The normally nonconducting transistor 282 also includes a collector electrode 296 connected to a negative source of potential, as for example minus 12 volts, through a second collector load resistor 298. Similarly, the emitter electrode 300 is connected to ground potential through a ground circuit 302 `by means of a conductor 304. The normally conducting transistor 280 further includes a base electrode 308 which is connected to a positive source of DC potential, as for example a positive 12 volts, through a resistor 310 in order to enhance the cutoff characteristics of the transistor 280. The base electrode 308 is also coupled to the collector electrode 296 through a conductor 312 and a coupling resistor 314. Thus, in the absence of an input signal, the current ow from the negative potential through resistor 298, resistor 314, conductor 312 and resistor 310 is suicient to negatively bias the base electrode 308, thereby maintaining transistor 280 in a conductive state.

The transistor 282 is also provided with a base electrode 320, which is coupled to the collector electrode 286 by means of a capacitor 322 and a resistor 324 combination, and a diode 326. With the single shot multivibrator in its stable state, the capacitor 322 is connected at the upper end thereof to a conductor 330, the resistor 324, the collector electrode 286 and emitter electrode 290 of transistor 280, conductor 294 to ground at 292. The opposite side of capacitor 322 is connected through a conductor 332, the diode 326, a conductor 334, a diode 336 to ground potential at ground connection 338. Thus the capacitor 322 is substantially in the discharge state.

When an input pulse switches normally conducting transistor 280 to the nonconductive state, the potential at node 340 between resistors 288 and collector electrode 286 `will drop to a minus 12 volts or logical zero level, thereby providing a charging circuit for capacitor 322 from negative 12 volt potential through resistor 288, resistor 324, capacitor 322, a resistor 344, to a positive 12 volt DC potential at terminal 346. With the switching of normally conducting transistor 280 to the nonconductive state, transistor 282 will switch to the conductive state, thereby raising the potential at collector electrode 296 from a rninus l2 volts to a zero volt potential or from a logical zero level to a logical one level. This logical one level output is fed from the collector electrode 296 through a conductor 346 to the output terminal 278. Similarly, transistor 280 switching from the conductive to the nonconductive state will cause node 340 to switch from a logical one level output signal to a logical zero level output signal. This voltage at node 340 is fed to the logical zero output terminal 276 by means of a conductor 348. The RC time constant of the charging circuit when the multivibrator is in the unstable state determines the duration of the output pulses generated on output terminals 276 and 278. While the circuit has been described as charging capacitor 322, it is to be understood that charging is generic to charging in one direction or the other, depending on the circuit parameters of the monostable circuit 270.

The base electrode 308 is connected through an input circuit 350 which consists of the input terminals 272, 274, a differentiating circuit 352 and a polarity selecting diode 354, in the preferred use of the single shot multivibrator 270. The input terminals 272 and 274 are normally maintained at a logical zero level and an input pulse fed thereto raises either of the input terminals 272,

274 to a logical one level. This input pulse is fed through the diodes 358, 360 to a node 362 where in the node 36-2 is connected to the minus 12 volt potential through a resistor 364 and to ground through a capacitor 366 and a resistor 368.

With the input terminals 272, 274, the minus 12 volt level or at a logical zero level, the node 362 also will be at a logical zero level, thereby charging the capacitor 366 through resistors 368 and 364. With the input pulse of a logical one level appearing at input terminals 272, 274, a capacitor `will provide a positive going and a negative going spike at a node 370, the positive half of which is fed to base electrode 308 through a diode 354. This positive spike back biases the base emitter circuit of transistor 280 thereby rendering the transistor 280 nonconductive. As described above, the single shot multivibrator 270 will be switched to its unstable state to produce output pulses at either of output terminals 276 or 278. A symbol 374 has been illustrated at the upper left portion of the ligure which is representative of the single shot multivibrator for purposes of this description.

Referring now to FIGURE 5, there is illustrated a high gain current amplifier circuit 3180 in the form of a Darlington power driver circuit configuration wherein a plurality of PNP transistors 382, 384 are connected between ground by means of a conductor 386 and an output terminal 388 through a load resistor 390. The amplifier circuit is utilized in providing a high current to a load such as the coil of a punch unit, or the like, wherein the transistors 382, 384 are utilized in switching the load current on and off. In the particular circuit illustrated, an emitter electrode 392 is connected to ground through conductor 386 and a base electrode 394 is connected to an emitter electrode 396 of the transistor 384. The collector electrode 398 is connected to the resistor 390 by means of a resistor 400i, and the collector electrode 402 of transistor 384 is connected to the resistor 390 by means of a conductor 404. The input circuit comprises an input terminal 406 connected through a diode 408 to a node 410. A series resistance path between a negative source of potential at terminal 412 and a positive source of potential at terminal 414 is provided by means of resistors 416, 418 and 420.

Thus, as the input signal drops from a logical one level to a logical zero level, the potential at node 410 `will drop from a logical one to a logical zero, thereby rendering the transistor 384 conductive. The conduction of transistor 384 will provide a conductive path for the emitterbase current of transistor 382 thereby rendering the transistor 382 conductive to provide a current path from the emitter to collector thereof and provide current ow for the load circuit connected to the output terminal 388. A diode 424 is connected between a node 426 and a source of negative potential, as for example, negative 24 volts at terminal 428 to provide arc suppression for the load circuit. A symbolic representation 428 of the power driver circuit has been illustrated above the schematic diagram.

Referring now to FIGURE 6, there is illustrated a transistor logic circuit 430, representatively illustrated as a norgate, wherein one or a plurality of input signals are fed to a plurality of input terminals 432, 434, 436 through diodes 438, 440, 442. An output terminal 444 is connected to a collector electrode 446 of a normally conducting transistor 448, in the normal use of the circuit in the system to be hereinafter described. The input terminals are maintained at a logical zero level and a true signal raises the input terminal to a logical one level. This rise in signal level from a logical zero to a logical one drops the output signal level at output termina] 444 from a logical one to a logical zero level, thereby providing an inversion of the input signal. This operation is maintained by the proper choice of magnitude of a plurality of resistors 450, 452, 454, which are connected between a source of negative potential at terminal 456 and n source of positive potential at terminal 458. The resistor 454 is chosen to be relatively large compared to resistors 450, 452, thereby maintaining a base electrode 460 of the transistor 448 at a relatively large negative potential with respect to its emitter electrode 462, the emitter electrode being connected to ground through a conductor 464.

With one of the input terminals at a logical one level, the juncture 468 between resistors 450 and 452 will rise to approximate a zero potential, or a logical one signal level, thereby rendering the base electrode 450 more positive and switching the transistor 448 to the nonconductive state. With the transistor 448 in a nonconductive state, the output terminal 444 is substantially at a minus 12 volt level or a logical zero level through the connection of the output terminal 444 to the source of negative l2 volt `potential through resistor 470. A symbol 474 for the norgate 430 has been illustrated at the upper portion of the ligure.

Referring now to FIGURE 7, there is illustrated a bistable pulsing circuit or switch trigger 480 having a first combination input and output terminal 482 and a second combination input and output terminal 484. The voltage at the first terminal 482 is controlled by means of a transistor `486 wherein an emitter electrode 488 is connected to ground through a conductor 490 and a collector electrode 492 is connected to a negative source of potential, as for example l2 volts, at a terminal 494 through a resistor 496. Thus the conduction of transistor 486 renders the output terminal at a logical one level and the nonconduction of transistor 486 renders the terminal 482 at the logical zero level. The second terminal 484 is similarly connected to a transistor 498 wherein an emitter electrode 500 thereof is connected to ground through a conductor 502 and a collector electrode 504 is connected to a negative potential at terminal 506 through a resistor 508. The nonconduction and conduction of transistor 498 renders the output terminal between a logical zero level and a logical one level, respectively.

The collector electrode 492 is connected to a base electrode 512 of transistor 498 through a coupling resistor 514 and a ibase electrode 516 is connected to the collector electrode 504 through a second coupling resistor 518. The base electrodes 512 and 516 are connected to a positive source of DC potential through resistors 522 and S24, respectively. Assuming transistor 486 to be initially conductive, the collector electrode 492 will be at approximately a logical one level thereby rendering the base electrode 512 at a potential very close to the potential of the emitter electrode 500. Thus the transistor 498 will be rendered nonconductive.

If a logical one signal is impressed on input/ output terminal 484, the transistor 486 will be rendered nonconductive thereby rendering transistor 498 conductive through the coupling path of resistor 514. Any further logical one pulses at input/output terminal 484 will be ineffective to switch the state of the switch trigger circuit 480, thus rendering the circuit unresponsive to a bouncing input signal at input/output terminal 484. Similarly, if a logical one signal is impressed on input/output terminal 482, the switch trigger circuit will again change in state `whereby transistor 484 is rendered conductive and transistor 498 is rendered nonconductive as in the above situation. Further, logical one signals at input/output terminal 482 will be inetective to change the state of the switch trigger circuit 480. A symbolic representation 530 of the switch trigger circuit has been illustrated at the upper portion of the FIGURE 7.

Referring now to FIGURE 8, there is illustrated a norgate similar to the norgate described in conjunction with FIGURE 6 and further including an integrating circuit in the input logic circuitry. As in the above norgate circuit 430, a plurality of input terminals 532, 534 and 536 are connected to an input node 538 through a plurality of diodes 540, 542, 544. An output terminal 546 is connected to a collector electrode 548 of a transistor 550 and an emitter electrode 552 is connected to ground through 

